Copyright(C) 1994,1995,1996,1997 Terumasa KODAKA , Takeshi KONO
■RS-232C
Target Normal, High Resolution, LT/HA
Chip 8251 equivalent
Explanation o PC-9800 series uses 8251USART as serial interface. In
asynchronous mode, the output of 8253TCU counter #2 is connected to the TXC
and RXC terminals of 8251USART, so the communication speed is set by the rate
of the square wave output by this counter. The clock input of 8253TCU counter
#2 is different for models with 8MHz and 5MHz system clocks. As a result, the
division ratio to be set to achieve the same communication speed will be
different depending on the system clock.
o In PC-9801P/NX/C, PC-9821Af/Ne and later models, the operating clock of
8251USART was changed from 2.4576MHz to 9.8304MHz. Communication speeds of
over 9600bps are guaranteed. However, this is only the official specification,
and as mentioned above, the communication speed is set by the output of the
8253TCU, so if you change the division ratio, it is possible to set the
communication speed to more than 9600bps even on machines that do not support
19200bps. However, in models with an 8MHz system clock, it is not possible to
set it to an exact multiple of 19200bps due to the division ratio. It is
possible to set it to a multiple of 20800bps as a close value, but peripheral
devices such as modems must support this communication speed.
u The BIOS of the PC-9801P/NX/C and PC-9821Ne does not support 19200bps, but
communication at 19200bps is guaranteed by directly manipulating the hardware
and setting the division ratio in the 8253TCU.
o PC-9821An (excluding some lots)/Np and later models are equipped with a FIFO
mode. It has a capacity of 16 bytes for sending and receiving, and it is
possible to reduce character dropouts during high-speed communication. In FIFO
mode, a different access method is required than before, and special code must
be written.
o Models equipped with a 16550 equivalent CCU as a second RS-232C can use
V･FAST mode, which allows transfer speeds of up to 115200bps, even on the
primary serial port. Even models that do not have a second RS-232C include a
16550 equivalent part inside the integrated I/O chip, and are used for
infrared communication interfaces, etc., so V･FAST mode can be used just like
models equipped with a secondary serial port.
Figure: RS-232C clock
--------------------------------------------------------------------
System +------------+ +------------+
Clock (*1) |Divided by 4| | 8253 TCU | #2 output
o------------>----------+ Circuit +--->---+ Counter #2 +---->---+
| (*2) | | (*3) | |
+------------+ +------------+ V
I/O 0434h bit 6 I/O 0075h,0077h |
|
+-----------------+ +---------+--------+
2ndCCU clock (*4) | V･FAST mode | |V･FAST, compatible|
o------>------+------>-----+Division register+----->-----+ Mode selection |
| | (*5) | | (*6) |
| +-----------------+ +---------+--------+
| I/O 013Ah bit 3-0 | I/O 013Ah bit 7
V V
| |
+-----+-----+ +----+----+
| 2nd CCU | | 1st CCU |
| 16550(*7) | | 8251 |
+-----+-----+ +----+----+
| |
*1 System clock. Can be 2.4576MHz or 1.98...MHz.
*2 Sets whether to divide the clock given to the 8253TCU counter #2 input by 4.
Available on 19200bps compatible devices.
*3 Sets the square wave rate of the clock output of counter #2 by manipulating
the divide register. Available on all devices.
*4 Clock to be supplied to the 2ndCCU 16550. Available on devices with V･FAST mode.
*5 Sets the speed in V･FAST mode. Available on devices with V･FAST mode.
*6 Sets whether to select V･FAST mode or compatible mode.
Available in models with V･FAST mode.
*7 Available in models with a secondary serial interface. In models with an
infrared interface, it is used to connect to an infrared transceiver unit.
--------------------------------------------------------------------
Related INT 0Bh
F8E8:0002h bit 2
F8E8:0011h bit 4
I/O 0002h bit 3
I/O 0033h bit 7〜6
I/O 0035h bit 2〜0
I/O 0075h
I/O 0077h
I/O 08F0h,08F2h - 0056h bit 0
I/O 0030h
Name Data register
Chip Equivalent to 8251
Function
[READ] Receive data register
[WRITE] Transmit data register
bit 7-0: Data
Description o Inputs and outputs data to be sent and received via the serial interface.
o For details, see the μPD71051 data sheet.
Related I/O 0032h
I/O 0032h
Name Status read
Mode set, command word write
Chip Equivalent to 8251
Function
[READ] Status read
bit 7: DSR signal
1 = DSR ON
0 = DSR OFF
bit 6: Synchronization detection
1 = Yes
0 = No
bit 5: Framing error detection
1 = Yes
0 = No
bit 4: Overrun error detection
1 = Yes
0 = No
bit 3: Parity error detection
1 = Yes
0 = No
bit 2: TxEMP
1 = Transmit buffer empty
0 = Data in transmit buffer
bit 1: RxRDY
1 = Receiving possible
0 = Receiving not possible
bit 0: TxRDY
1 = Free space in transmit buffer
0 = No space in transmit buffer
-----+-----+----------------+--------------+------------
TxEMP|TxRDY| Buffer #0 | Buffer #1 | Send data
-----+-----+----------------+--------------+------------
1 | 1 | No data | No data | Can be sent
0 | 1 | Data present | No data | Can be sent
0 | 0 | Data present | Data present | Cannot be sent
1 | 0 | Does not exist
-----+-----+----------------+--------------+------------
[WRITE] Write command word
bit 7: Enter hunt phase (synchronous mode only)
bit 6: Internal reset
1 = Yes
0 = No
bit 5: RTS signal
1 = RTS ON
0 = RTS OFF
bit 4: Clear error flag
1 = Yes
0 = No
bit 3: Send TxDATA break
1 = Yes
0 = No
bit 2: Receive enable
1 = Enable
0 = Disable
bit 1: DTR signal
1 = DTR ON
0 = DTR OFF
bit 0: Send enable
1 = Enable
0 = Disable
[WRITE] Mode set
bit 7,6: S2,S1
11b = 2 bits
10b = 1.5 bits
01b = 1 bit
00b = Disable
* Sets the stop bit length
bit 5: EP
1 = Even parity
0 = Odd parity
bit 4: PEN
1 = With parity
0 = Without parity
bit 3,2: L2,L1
11b = 8 bits
10b = 7 bits
01b = 6 bits
00b = 5 bits
* Sets the data bit length
bit 1,0: B2,B1
11b = x64 mode
10b = x16 mode
01b = x1 mode
00b = synchronous mode
* Sets the clock mode
Description o Sets various modes for the serial interface.
o For details, see the μPD71051 data sheet.
Related I/O 0030h
I/O 0034h
Name Extended interrupt control register
Undocumented
Target PC-9821Af and later
Function
[READ/WRITE]
bit 7: Interrupt mode
1 = Signal line change interrupt
0 = Previously compatible (default)
* In signal line change interrupt mode, the previous interrupts caused by
TxRDY, TxEMP, and RxRDY are not generated.
bit 6: Unused (always set to 0)
bit 5: CD signal interrupt
bit 4: DSR signal interrupt
bit 3: CTS signal interrupt
1 = Interrupt enabled
0 = Interrupt disabled (default)
* Sets whether to detect the edge of each signal and generate an interrupt.
bit 2: CD signal ■ [READ]
bit 1: DSR signal ■ [READ]
bit 0: CTS signal ■ [READ]
1 = Enable
0 = Disable
* These are the same signals as those obtained by I/O 0033h bits 7 to 5.
Description o Sets whether to generate an interrupt when the serial port signal line changes.
Related I/O 0030h
I/O 0032h
I/O 0033h
I/O 0434h
I/O 0130h
Name Transmit/Receive Data Register
Undocumented
Target Devices with FIFO mode
Function
[READ/WRITE]
Bit 7-0: Data
Explanation o In FIFO mode, inputs and outputs data to be transmitted and
received via the serial interface.
Corresponds to I/O 0030h in conventional compatibility mode.
o The FIFO capacity is 16 bytes.
o This I/O is only valid in FIFO mode.
Related I/O 0030h
I/O 0138h bit 0
I/O 0132h
Name Line Status Register
Undocumented
Target FIFO mode equipped devices
Function
[READ]
bit 7: Break signal received
1 = Received
0 = Normal
bit 6: Unknown
bit 5: Parity error
1 = Error
0 = Normal
bit 4: Overrun error
1 = Error
0 = Normal
bit 3: Unknown
bit 2: RxRDY
1 = Ready
0 = Busy
bit 1: TxRDY
1 = Ready
0 = Busy
bit 0: TxEMP
1 = Empty
0 = Normal
Description o In FIFO mode, obtains the status of various signal lines of the serial interface.
o Details unknown
Related I/O 0138h bit 0
I/O 0134h
Name Modem status register
Undocumented
Target FIFO mode equipped devices
Function
[READ]
bit 7: CD signal
bit 6: CI signal
bit 5: DR signal
bit 4: CS signal
1 = ON
0 = OFF
bit 3: CD signal change
bit 2: CI signal change
bit 1: DR signal change
bit 0: CS signal change
1 = Changed
0 = No change
Explanation o Reads the modem status signal.
o Details unknown
Related I/O 0034h
I/O 0138h bit 0
I/O 0136h
Name Interrupt reference register
Undocumented
Target FIFO mode equipped devices
Function
[READ]
bit 7: Unknown
bit 6: FIFO equipped identification bit 1
* Changes from 1 to 0 to 1 to ... each time it is read
bit 5: Identification bit 2
* Always returns 0
bit 4: Unknown
bit 3-0: Interrupt cause index
111b =
110b = Received data present (timeout)
101b =
100b =
011b = Line status change
010b = Received data present
001b = Transmission possible
000b = Modem status change
* Indicates interrupt cause
bit 0: Interrupt cause
1 = None
0 = Present
Explanation o Gets the interrupt cause. Also, bits 6 and 5 can be used to
determine whether the device is equipped with a FIFO.
o Details unknown
Related
I/O 0138h
Name FIFO control register
Undocumented
Target FIFO mode equipped devices
Function
[READ/WRITE]
bit 7-3: Unknown
bit 6: Unknown
bit 2: FCR2
1 = Reset transmit FIFO
0 = Do not reset transmit FIFO
bit 1: FCR1
1 = Reset receive FIFO
0 = Do not reset receive FIFO
bit 0: FCR0
1 = FIFO mode
0 = Legacy compatible mode (default)
Explanation o Sets the FIFO for RS-232C.
o FIFO mode requires a different access method than the conventional serial
interface. FIFO mode and legacy compatible mode can be changed dynamically.
Related I/O 0030h
I/O 0032h
I/O 013Ah
Name V･FAST mode register
Undocumented
Target 115200bps compatible devices
Function
[READ/WRITE]
bit 7: Clock mode
1 = V･FAST mode
0 = Conventional compatibility mode
bit 6-4: Unused (always set to 000b)
bit 3-0: Frequency division register
1100b = 9600bps
1000b = 14400bps
0110b = 19200bps
0100b = 28800bps
0011b = 38400bps
0010b = 57600bps
0001b = 115200bps
* Only valid when bit 7 is 1
Explanation o Sets the communication speed of the primary serial interface.
o When V･FAST mode is set with bit 7, the communication speed is set
regardless of the 8253TCU counter #2 output. In this case, the communication
speed is determined by bits 3 to 0.
u It can be assumed that the name V･FAST mode comes from the fact that it was
set to support modems with speeds of 28,800 bps or more, but there is no
direct relationship between V･FAST modems and communication methods, etc.
Related I/O 0411h,0413h - 83h
F8E8:0011h bit 4
I/O 0434h
Name Extended RS-232C control register
Undocumented
Target PC-9821■[Excluding PC-9821 original, Ap, As, Ae, Ce]
PC-9801BA2, BS2, BX2, BA3, BX3, BX4, P, NS/A, NL/A
Function
[READ/WRITE]
bit 7: Unused
bit 6: Input clock divided by 4■[PC-9821An, Ap3, As3, Xa, Xt, Xf, Cf, Xa16,
Xa13, Xa12, Xa10, Xa9, Xa7, Xa7e, Xt16, Xt13, Except Xv13, Xb10, V10, V7,
St15, Na7, Nx]
1 = No
0 = Yes (default)
* Can be set to 4x speed mode
bit 6: Input clock divided by 4■[PC-9821An･Ap3･As3･Xa･Xt･Xf･Cf･Xa10･Xa9･Xa7･Xt13･Xa12･Xa7e･Na7･Nx]
1 = No (default)
0 = Yes
* Can be set to 1/4x speed mode
| [Note]
| Mr. Takeshi Aida pointed out that the following content may be correct (1999/2/10)
| 1 = Yes (default)
| 0 = No
bit 5-1: Unused
bit 0: Disconnect primary serial port
1 = Disconnect
0 = Do not disconnect (default)
Explanation o Sets the clock mode of the primary serial port.
o Disconnects the primary serial interface.
Related I/O 0030h
I/O 0032h
I/O 0034h
I/O 0130h
I/O 0132h
I/O 0134h
I/O 0136h
I/O 0138h
I/O 013Ah
-------------------------------------------------------------------------------
■Extended RS-232C board control
Target PC-9861, PC-9801-101
Explanation o PC-9861･K is a board equipped with two extended RS-232C ports.
It uses an 8251A equivalent and can be used in almost the same way as the main
unit's built-in primary serial port.
u On the PC-9861･K, the transfer speed is set by a jumper switch on the board.
o PC-9801-101 can use FIFO mode
I/O 00B0h
Name Extended RS-232C Channel 2 Control
Function
[READ] Read signal
bit 7: CI
bit 6: CS
bit 5: CD
bit 4-0: Unused
[READ] Interrupt level sense
bit 7-2: Unused
bit 1,0: IR1,IR2
11b = INT3
10b = INT2
01b = INT1 (High-resolution mode standard setting)
00b = INT0 (Factory setting)
[WRITE] Mask set
bit 7-3: Unused
bit 2: TXR Mask interrupt request by RS-232C TxRDY
bit 1: TXE Mask interrupt request by RS-232C TxEMP
bit 0: RXR Masking interrupt requests by RS-232C RxRDY
Explanation o Reads the signal line of extended RS-232C channel 2, controls interrupt masks, etc.
Related I/O 00B2h
I/O 00B3h
I/O 00B2h
Name Extended RS-232C Channel 3 Control
Function
[READ] Read signal
bit 7: CI
bit 6: CS
bit 5: CD
bit 4-0: Unused
[READ] Interrupt level sense
bit 7-2: Unused
bit 1,0: IR1,IR2
11b = INT6
10b = INT5 (factory setting)
01b = INT4
00b = INT0 (standard setting for high-resolution mode)
[WRITE] Mask set
bit 7-3: Unused
bit 2: TXR Mask interrupt request by RS-232C TxRDY
bit 1: TXE Mask interrupt request by RS-232C TxEMP
bit 0: RXR Masking interrupt requests by RS-232C RxRDY
Explanation o Reads the signal line of extended RS-232C channel 3, controls interrupt masks, etc.
Related I/O 00BAh
I/O 00BBh
I/O 00B1h
Name Extended RS-232C Channel 2 Data
Chip Equivalent to 8251
Function
[READ] Receive Data Register
[WRITE] Transmit Data Register
bit 7-0: Data
Explanation o Inputs and outputs data to be sent and received via the serial interface.
o For details, see the μPD71051 data sheet.
Related I/O 00B3h
I/O 00B3h
Name Extended RS-232C channel 2
Status read, mode set, command word write
Chip Equivalent to 8251
Function
[READ] Status read
bit 7: DSR signal
1 = DSR ON
0 = DSR OFF
bit 6: Synchronization detection
1 = Yes
0 = No
bit 5: Framing error detection
1 = Yes
0 = No
bit 4: Overrun error detection
1 = Yes
0 = No
bit 3: Parity error detection
1 = Yes
0 = No
bit 2: TxEMP
1 = Transmit buffer empty
0 = Data in transmit buffer
bit 1: RxRDY
1 = Receiving possible
0 = Not receiving
bit 0: TxRDY
1 = Free space in transmit buffer
0 = No free space in transmit buffer
-----+-----+--------------+--------------+--------------
TxEMP|TxRDY|Buffer #0 | Buffer #1 | Transmit data
-----+-----+--------------+--------------+--------------
1 | 1 | No data | No data | Possible
0 | 1 | Data present | No data | Possible
0 | 0 | Data present | Data present | Not possible
1 | 0 | Does not exist
-----+-----+--------------+--------------+--------------
[WRITE] Write command word
bit 7: Enter hunt phase (synchronous mode only)
bit 6: Reset
1 = Yes
0 = No
bit 5: RTS signal
1 = RTS ON
0 = RTS OFF
bit 4: Clear error flag
1 = Yes
0 = No
bit 3: Transmit TxDATA break
1 = Yes
0 = Not enabled
bit 2: Receive enabled
1 = Enabled
0 = Disabled
bit 1: DTR signal
1 = DTR ON
0 = DTR OFF
bit 0: Send enabled
1 = Enabled
0 = Disabled
[WRITE] Mode set
bit 7,6: S2,S1
11b = 2 bits
10b = 1.5 bits
01b = 1 bit
00b = Disabled
* Sets the stop bit length
bit 5: EP
1 = Even parity
0 = Odd parity
bit 4: PEN
1 = With parity
0 = Without parity
bit 3,2: L2,L1
11b = 8 bits
10b = 7 bits
01b = 6 bits
00b = 5 bits
* Sets the data bit length
bit 1,0: B2,B1
11b = x64 mode
10b = x16 mode
01b = x1 mode
00b = synchronous mode
* Sets the clock mode
Description o Sets various modes for the serial interface.
o For details, see the μPD71051 data sheet, etc.
Related I/O 00B2h
I/O 00B4h
Name Extended RS-232C Channel 2 FIFO Control [INDEX]
Target PC-9801-101
Function
[READ/WRITE]
bit 7-0: Register
Explanation o Together with I/O 00B5h, this controls the FIFO of extended RS-232C channel 2.
o Details unknown.
Related I/O 00B5h
I/O 00B5h
Name Extended RS-232C Channel 2 FIFO Control [DATA]
Undocumented
Target PC-9801-101
Function
[READ/WRITE]
bit 7-0: Data
---------+----------------------------------------------
Register | Contents
---------+----------------------------------------------
00h | Transmit/Receive Data Register
| bit 7-0: Data
---------+----------------------------------------------
01h | Line Status Register
| bit 7: Break Signal Received
| 1 = Received
| 0 = Normal
| bit 6: Unknown
| bit 5: Parity Error
| 1 = Error
| 0 = Normal
| bit 4: Overrun Error
| 1 = Error
| 0 = Normal
| bit 3: Unknown
| bit 2: RxRDY
| 1 = Ready
| 0 = Busy
| bit 1: TxRDY
| 1 = Ready
| 0 = Busy
| bit 0: TxEMP
| 1 = Empty
| 0 = Normal
---------+----------------------------------------------
02h | Modem Status Register
| bit 7: CD signal
| bit 6: CI signal
| bit 5: DR signal
| bit 4: CS signal
| 1 = ON
| 0 = OFF
| bit 3: CD signal change
| bit 2: CI signal change
| bit 1: DR signal change
| bit 0: CS signal change
| 1 = Changed
| 0 = No change
---------+----------------------------------------------
03h | Interrupt Reference Register
| bit 7: Unknown
| bit 6: FIFO equipped identification bit 1
| * Changes from 1 to 0 to 1 to ... each time it is read
| bit 5: Identification bit 2
| * Always returns 0
| bit 4: Unknown
| bit 3-0: Interrupt cause index
| 111b =
| 110b = Received data available (timeout)
| 101b =
| 100b =
| 011b = Line status change
| 010b = Received data available
| 001b = Transmission possible
| 000b = Modem status change
| * Indicates interrupt cause
| bit 0: Interrupt cause
| 1 = No
| 0 = Yes
---------+----------------------------------------------
04h | FIFO control register
| bit 7-3: Unknown
| bit 6: Unknown
| bit 2: FCR2
| 1 = Transmit FIFO reset
| 0 = Transmit FIFO not reset
| bit 1: FCR1
| 1 = Receive FIFO reset
| 0 = Receive FIFO not reset
| bit 0: FCR0
| 1 = FIFO mode
| 0 = Compatible with previous mode (default)
---------+----------------------------------------------
05h | Communication speed setting register
| bit 7,6: Unknown
| bit 5,4: Communication method
| 11b = BCI synchronous
| 10b = Synchronous clock
| 01b = ST2 synchronous
| 00b = Asynchronous (default)
| bit 3-0: Communication speed
| 1111b = 115200bps
| 1110b = 57600bps
| 1101b = 38400bps
| 1100b = 19200bps
| 1011b = 14400bps
| 1010b = 9600bps
| 1001b = 4800bps
| 1000b = 2400bps
| 0111b = 1200bps
| 0110b = 600bps
| 0101b = 300bps
| 0100b = 150bps
| 0011b = 75bps
| * Only valid when DIP SW 2-2 is ON
---------+----------------------------------------------
06h | Unknown
---------+----------------------------------------------
07h | Unknown
---------+----------------------------------------------
Explanation o Reads and writes the FIFO control register of the extended
RS-232C channel 2 specified by I/O 00B4h.
o Details unknown.
Related I/O 00B4h
I/O 00B6h
Name Extended RS-232C Channel 2 FIFO Control [INDEX]
Target PC-9801-101
Function
[READ/WRITE]
bit 7-0: Register
Explanation o Together with I/O 00B7h, this controls the FIFO of extended RS-232C channel 2.
o Details unknown.
Related I/O 00B7h
I/O 00B7h
Name Extended RS-232C Channel 2 FIFO Control [DATA]
Undocumented
Target PC-9801-101
Function
[READ/WRITE]
[READ/WRITE]
bit 7-0: Data
---------+----------------------------------------------
Register | Contents
---------+----------------------------------------------
00h | Transmit/Receive Data Register
| bit 7-0: Data
---------+----------------------------------------------
01h | Line Status Register
| bit 7: Break Signal Received
| 1 = Received
| 0 = Normal
| bit 6: Unknown
| bit 5: Parity Error
| 1 = Error
| 0 = Normal
| bit 4: Overrun Error
| 1 = Error
| 0 = Normal
| bit 3: Unknown
| bit 2: RxRDY
| 1 = Ready
| 0 = Busy
| bit 1: TxRDY
| 1 = Ready
| 0 = Busy
| bit 0: TxEMP
| 1 = Empty
| 0 = Normal
---------+----------------------------------------------
02h | Modem status register
| bit 7: CD signal
| bit 6: CI signal
| bit 5: DR signal
| bit 4: CS signal
| 1 = ON
| 0 = OFF
| bit 3: CD signal change
| bit 2: CI signal change
| bit 1: DR signal change
| bit 0: CS signal change
| 1 = Changed
| 0 = No change
---------+----------------------------------------------
03h | Interrupt reference register
| bit 7: Unknown
| bit 6: FIFO equipped identification bit 1
| * Changes from 1 to 0 to 1 to ... each time it is read
| bit 5: Identification bit 2
| * Always returns 0
| bit 4: Unknown
| bit 3-0: Interrupt cause index
| 111b =
| 110b = Received data present (timeout)
| 101b =
| 100b =
| 011b = Line status change
| 010b = Received data present
| 001b = Transmission possible
| 000b = Modem status change
| * Indicates interrupt cause
| bit 0: Interrupt cause
| 1 = None
| 0 = Present
---------+----------------------------------------------
04h | FIFO control register
| bit 7-3: Unknown
| bit 6: Unknown
| bit 2: FCR2
| 1 = Reset transmit FIFO
| 0 = Not reset transmit FIFO
| bit 1: FCR1
| 1 = Reset receive FIFO
| 0 = Not reset receive FIFO
| bit 0: FCR0
| 1 = FIFO mode
| 0 = Legacy compatible mode (default)
---------+----------------------------------------------
05h | Communication speed setting register
| bit 7,6: Unknown
| bit 5,4: Communication method
| 11b = BCI synchronous
| 10b = Synchronous clock
| 01b = ST2 synchronous
| 00b = Asynchronous (default)
| bit 3-0: Communication speed
| 1111b = 115200bps
| 1110b = 57600bps
| 1101b = 38400bps
| 1100b = 19200bps
| 1011b = 14400bps
| 1010b = 9600bps
| 1001b = 4800bps
| 1000b = 2400bps
| 0111b = 1200bps
| 0110b = 600bps
| 0101b = 300bps
| 0100b = 150bps
| 0011b = 75bps
| * Only valid when DIP SW 2-2 is ON
---------+----------------------------------------------
06h | Unknown
---------+----------------------------------------------
07h | Unknown
---------+----------------------------------------------
Explanation o Reads and writes the FIFO control register of the extended RS-232C channel 3 specified by I/O 00B6h.
o Details unknown.
Related I/O 00B6h
I/O 00B8h
Name Extended RS-232C board control
Undocumented
Target PC-9801-101
Function
[READ]
Bit 7-5: Unknown
Bit 4: EEPROM DO signal
Bit 3: DIP-SW 2-2
1 = OFF
0 = ON
* Communication speed can be set when ON)
Bit 2: DIP-SW 2-1
1 = OFF
0 = ON
* Shared interrupt mode when ON
Bit 1: CH3 interrupt factor flag
Bit 0: CH2 interrupt factor flag
1 = Yes
0 = No
* Only valid in shared interrupt mode
[WRITE]
Bit 7-0: Unknown
Explanation o Controls the extended RS-232C board.
o Details unknown
Related I/O 00B4h, 00B5h - 05h
I/O 00B6h, 00B7h - 05h
I/O 00BAh
I/O 00B9h
Name Extended RS-232C channel 3 data
Chip Equivalent to 8251
Function
[READ] Receive data register
[WRITE] Transmit data register
bit 7-0: Data
Explanation o Inputs and outputs data to be sent and received via the serial interface.
o For details, see the μPD71051 data sheet.
Related I/O 00BBh
I/O 00BAh
Name Extended RS-232C board control
Undocumented
Target PC-9801-101
Function
[READ]
Bit 7-3: Unknown
Bit 2: EEPROM CS signal
Bit 1: EEPROM SK signal
Bit 0: EEPROM DI signal
Explanation o Controls the EEPROM that stores the Plug and Play information of the extended RS-232C board.
Details unknown
Related I/O 0259h,0A59h
I/O 00B8h
I/O 00BBh
Name Extended RS-232C channel 3
Status read, mode set, command word write
Chip Equivalent to 8251
Function
[READ] Status read
bit 7: DSR signal
1 = DSR ON
0 = DSR OFF
bit 6: Synchronization detection
1 = Yes
0 = No
bit 5: Framing error detection
1 = Yes
0 = No
bit 4: Overrun error detection
1 = Yes
0 = No
bit 3: Parity error detection
1 = Yes
0 = No
bit 2: TxEMP
1 = Transmit buffer empty
0 = Data in transmit buffer
bit 1: RxRDY
1 = Receiving possible
0 = Receiving not possible
bit 0: TxRDY
1 = Free space in transmit buffer
0 = No space in transmit buffer
-----+-----+-----------------+--------------+------------
TxEMP|TxRDY| Buffer #0 | Buffer #1 |Send data
-----+-----+-----------------+--------------+------------
1 | 1 | No data | No data | Can be sent
0 | 1 | Data present | No data | Can be sent
0 | 0 | Data present | Data present | Cannot be sent
1 | 0 | Does not exist
-----+-----+-----------------+--------------+------------
[WRITE] Write command word
bit 7: Enter hunt phase (synchronous mode only)
bit 6: Reset
1 = Yes
0 = No
bit 5: RTS signal
1 = RTS ON
0 = RTS OFF
bit 4: Clear error flag
1 = Yes
0 = No
bit 3: Send TxDATA break
1 = Yes
0 = No
bit 2: Receive enable
1 = Enable
0 = Disable
bit 1: DTR signal
1 = DTR ON
0 = DTR OFF
bit 0: Send enable
1 = Enable
0 = Disable
[WRITE] Mode set
bit 7,6: S2,S1
11b = 2 bits
10b = 1.5 bits
01b = 1 bit
00b = Disable
* Sets the stop bit length
bit 5: EP
1 = Even parity
0 = Odd parity
bit 4: PEN
1 = With parity
0 = Without parity
bit 3,2: L2,L1
11b = 8 bits
10b = 7 bits
01b = 6 bits
00b = 5 bits
* Sets the data bit length
bit 1,0: B2,B1
11b = x64 mode
10b = x16 mode
01b = x1 mode
00b = synchronous mode
* Sets the clock mode
Description o Sets various modes for the serial interface.
o For details, see the μPD71051 data sheet, etc.
Related I/O 00BAh